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1 ltc1326/ltc1326-2.5 micropower precision triple supply monitors rst output voltage vs supply voltage (ltc1326-2.5) n simultaneously monitors three supplies ltc1326: 5v, 3.3v and adj ltc1326-2.5: 2.5v, 3.3v and adj n guaranteed threshold accuracy: 0.75% n low supply current: 20 m a n internal reset time delay: 200ms n manual push-button reset input n active low and active high reset outputs n active low soft reset output n power supply glitch immunity n guaranteed reset for v cc3 3 1v or v cc5 3 1v or v cc25 3 1v n 8-pin so and msop packages features the ltc ? 1326/ltc1326-2.5 are triple supply monitors intended for systems with multiple supply voltages. they provide micropower operation, small size and high accu- racy supply monitoring. tight 0.75% threshold accuracy and glitch immunity ensure reliable reset operation without false triggering. the 20 m a typical supply current makes the ltc1326/ ltc1326-2.5 ideal for power-conscious systems. the rst output is guaranteed to be in the correct state for v cc3 , v cc5 or v cc25 down to 1v. the ltc1326/ltc1326-2.5 can be configured to monitor one, two or three inputs, depending on system requirements. a manual push-button reset input provides the ability to generate a very narrow soft reset pulse (100 m s typ) or a 200ms reset pulse equivalent to a power-on reset. both srst and rst outputs are open-drain and can be or-tied with other reset sources. , ltc and lt are registered trademarks of linear technology corporation. descriptio u typical applicatio u n desktop computers n notebook computers n intelligent instruments n portable battery-powered equipment applicatio s u v cc3 (v) 0 2.0 2.5 3.5 1.5 2.5 1326/2.5 ta02 1.5 1.0 0.5 1.0 2.0 3.0 3.5 0.5 0 3.0 rst output voltage (v) v cc25 = v cca = v cc3 4.7k pull-up from rst to v cc3 t a = 25 c push-button reset 1326/2.5 ta01 v cc3 v cc25 0.1 m f v cca gnd rst pbr srst ltc1326-2.5 v core 3.3v 2.5v dc/dc converter system logic
2 ltc1326/ltc1326-2.5 a u g w a w u w a r b s o lu t exi t i s (notes 1, 2) terminal voltage v cc3 , v cc5 , v cc25 , v cca ......................... C 0.5v to 7v rst, srst ............................................ C 0.5v to 7v rst ...................................... C 0.5v to (v cc3 + 0.3v) pbr .......................................................... C 7v to 7v operating temperature range ltc1326c/ltc1326c-2.5 ....................... 0 c to 70 c ltc1326i/ltc1326i-2.5 ..................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c wu u package / o rder i for atio order part number order part number s8 part number 1326 1326i ltba ltc1326cs8 ltc1326is8 ltc1326cms8 ms8 part number v cc3 = 3.3v, v cc5 = 5v (for ltc1326),v cc25 = 2.5v (for ltc1326-2.5), v cca = v cc3 , t a = 25 c unless otherwise noted. symbol parameter conditions min typ max units v rt3 reset threshold v cc3 0 c t a 70 c l 3.094 3.118 3.143 v C40 c t a 85 c l 3.052 3.118 3.143 v v rt5 reset threshold v cc5 (ltc1326) 0 c t a 70 c l 4.687 4.725 4.762 v C40 c t a 85 c l 4.625 4.725 4.762 v v rt25 reset threshold v cc25 (ltc1326-2.5) 0 c t a 70 c l 2.344 2.363 2.381 v C40 c t a 85 c l 2.312 2.363 2.381 v v rta reset threshold v cca 0 c t a 70 c l 0.992 1.000 1.007 v C40 c t a 85 c l 0.980 1.000 1.007 v v cc v cc3 operating voltage rst in correct logic state l 17v i vcc3 v cc3 supply current pbr = v cc3 l 20 40 m a electrical characteristics order part number order part number s8 part marking ms8 part marking ltc1326cs8-2.5 ltc1326is8-2.5 ltc1326cms8-2.5 132625 326i25 ltek consult factory for military grade parts. 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so v cc3 v cc5 v cca gnd pbr srst rst rst t jmax = 125 c, q ja = 150 c/w 1 2 3 4 v cc3 v cc5 v cca gnd 8 7 6 5 pbr srst rst rst top view ms8 package 8-lead plastic msop t jmax = 125 c, q ja = 250 c/w 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so v cc3 v cc25 v cca gnd pbr srst rst rst t jmax = 125 c, q ja = 150 c/w 1 2 3 4 v cc3 v cc25 v cca gnd 8 7 6 5 pbr srst rst rst top view ms8 package 8-lead plastic msop t jmax = 125 c, q ja = 250 c/w
3 ltc1326/ltc1326-2.5 i vcc5 v cc5 input current (ltc1326) v cc5 = 5v l 47 m a i vcc25 v cc25 input current (ltc1326-2.5) v cc25 = 2.5v l 2.8 7 m a i vcca v cca input current v cca = 1v 0 c t a 70 c l C5 0 5 na C40 c t a 85 c l C15 0 15 na t rst reset pulse width rst low with 10k w pull-up to v cc3 0 c t a 70 c l 140 200 280 ms C40 c t a 85 c l 140 200 300 ms t srst soft reset pulse width srst low with 10k w pull-up to v cc3 l 50 100 200 m s t uv v cc undervoltage detect to rst v cc25 , v cc3 or v cca less than reset 13 m s threshold v rt by more than 1% i pbr pbr pull-up current pbr = 0v 0 c t a 70 c l 3710 m a C40 c t a 85 c l 3715 m a v il pbr, rst input low voltage l 0.8 v v ih pbr, rst input high voltage l 2v t pw pbr min pulse width l 40 ns t db pbr debounce deassertion of pbr input to srst l 20 35 ms output (pbr pulse width = 1 m s) t pb pbr assertion time for transition pbr held less than v il from soft to hard reset mode 0 c t a 70 c l 1.4 2.0 2.8 s C40 c t a 85 c l 1.4 2.0 3.0 s v ol rst output voltage low i sink = 5ma l 0.15 0.4 v i sink = 100 m a, v cc3 = 1v, v cc5 = 0v l 0.05 0.4 v 0 c t a 70 cv cc3 = 0v, v cc5 = 1v l 0.05 0.4 v v cc3 = 1v, v cc5 = 1v l 0.05 0.4 v i sink = 100 m a, v cc3 = 1.1v, v cc5 = 0v l 0.05 0.4 v C40 c t a 85 cv cc3 = 0v, v cc5 = 1.1v l 0.05 0.4 v v cc3 = 1.1v, v cc5 = 1.1v l 0.05 0.4 v i sink = 100 m a, v cc3 = 1v, v cc25 = 0v l 0.05 0.4 v 0 c t a 70 cv cc3 = 0v, v cc25 = 1v l 0.05 0.4 v v cc3 = 1v, v cc25 = 1v l 0.05 0.4 v i sink = 100 m a, v cc3 = 1.1v, v cc25 = 0v l 0.05 0.4 v C40 c t a 85 cv cc3 = 0v, v cc25 = 1.1v l 0.05 0.4 v v cc3 = 1.1v, v cc25 = 1.1v l 0.05 0.4 v srst output voltage low i sink = 2.5ma l 0.15 0.4 v rst output voltage low i sink = 2.5ma l 0.15 0.4 v v oh rst output voltage high (note 3) i source = 1 m a l v cc3 C 1 v srst output voltage high (note 3) i source = 1 m a l v cc3 C 1 v rst output voltage high i source = 600 m a l v cc3 C 1 v t phl prop delay rst to rst c rst = 20pf 25 ns high input to low output t plh prop delay rst to rst c rst = 20pf 45 ns low input to high output electrical characteristics v cc3 = 3.3v, v cc5 = 5v (for ltc1326),v cc25 = 2.5v (for ltc1326-2.5), v cca = v cc3 , t a = 25 c unless otherwise noted. symbol parameter conditions min typ max units
4 ltc1326/ltc1326-2.5 electrical characteristics ltc1326 only v cc3 = 3.3v, v cc5 = 5v, v cca = v cc3 , t a = 25 c unless otherwise noted. symbol parameter conditions min typ max units v ovr v cc5 reset override voltage override v cc5 ability to assert rst (note 4) v cc3 0.025 v note 3: the output pins srst and rst have weak internal pull-ups to v cc3 of 6 m a typ. however, external pull-up resistors may be used when faster rise times are required. note 4: the v cc5 reset override voltage is valid for an operating range less than approximately 4.15v. above this point the override is turned off and the v cc5 pin functions normally. the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. typical perfor a ce characteristics uw temperature ( c) 15 i vcc3 ( m a) 16 18 19 20 25 22 1326 /2.5 g01 17 23 24 21 ?0 ?0 20 40 ?0 0 60 80 100 i vcc3 vs temperature temperature ( c) 2.50 i vcc25 ( m a) 2.55 2.65 2.70 2.75 3.00 2.85 1326 /2.5 g03 2.60 2.90 2.95 2.80 ?0 ?0 20 40 ?0 0 60 80 100 i vcc25 vs temperature (ltc1326-2.5) temperature ( c) i vcc5 ( m a) 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 1326 /2.5 g02 ?0 ?0 20 40 ?0 0 60 80 100 i vcc5 vs temperature (ltc1326) v cc5 transient immunity (ltc1326) v cc5 reset comparator overdrive (v) 0.001 20 transient duration ( m s) 25 30 35 40 0.01 0.1 1 1326/2.5 g05 15 10 5 0 45 50 reset occurs above curve t a = 25 c v cca input current vs input voltage input voltage (v) 0.8 ? input current (na) ? ? 0 1 0.9 1.0 1.1 1.2 1326 /2.5 g04 2 3 0.85 0.95 1.05 1.15 t a = 25 c v cc25 transient immunity (ltc1326-2.5) v cc25 reset comparator overdrive (v) 0.001 transient duration ( m s) 0.01 0.1 1 1326/2.5 g06 45 40 35 30 25 20 15 10 5 0 reset occurs above curve t a = 25 c
5 ltc1326/ltc1326-2.5 typical perfor a ce characteristics uw temperature ( c) ?0 v cc25 threshold voltage, v rt25 (v) 2.375 2.370 2.365 2.360 2.355 2.350 ?0 20 40 1326 /2.5 g10 ?0 0 60 80 100 v cc25 threshold voltage vs temperature (ltc1326-2.5) temperature ( c) ?0 v cca threshold voltage, v rta (v) 1.005 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 ?0 20 40 1326 /2.5 g12 ?0 0 60 80 100 v cca threshold voltage vs temperature v cc3 threshold voltage vs temperature temperature ( c) ?0 v cc3 threshold voltage, v rt3 (v) 60 1326 /2.5 g11 ?0 20 ?0 80 0 40 100 3.135 3.130 3.125 3.120 3.115 3.110 3.105 3.100 reset pulse width vs temperature pbr assertion time to reset vs temperature soft reset pulse width vs temperature temperature ( c) 210 215 220 1326 /2.5 g13 205 200 195 190 reset pulse width, t rst (ms) 225 ?0 ?0 20 40 ?0 0 60 80 100 temperature ( c) 105.0 107.5 110.0 1326 /2.5 g14 102.5 100.0 97.5 95.0 soft reset pulse width, t srst ( m s) 112.5 ?0 ?0 20 40 ?0 0 60 80 100 temperature ( c) 2.10 2.15 2.20 1326 /2.5 g15 2.05 2.00 1.95 1.90 pbr assertion time to reset, t pb (sec) 2.25 ?0 ?0 20 40 ?0 0 60 80 100 v cca transient immunity v cca reset comparator overdrive (v) 0.001 20 transient duration ( m s) 30 40 0.01 0.1 1 1326/2.5 g07 10 0 25 35 15 5 reset occurs above curve t a = 25 c v cc3 reset comparator overdrive (v) 0.001 20 transient duration ( m s) 30 40 0.01 0.1 1 1326/2.5 g08 10 0 25 35 15 5 reset occurs above curve t a = 25 c v cc3 transient immunity temperature ( c) ?0 v cc5 threshold voltage, v rt5 (v) 4.750 4.745 4.740 4.735 4.730 4.725 4.720 4.715 4.710 4.705 4.700 ?0 20 40 1326 /2.5 g09 ?0 0 60 80 100 v cc5 threshold voltage vs temperature (ltc1326)
6 ltc1326/ltc1326-2.5 rst (pin 6): reset logic output. active low, open-drain logic output with weak pull-up to v cc3 . can be pulled up greater than v cc3 when interfacing to 5v logic. asserted when one or more of the supplies are below trip thresholds and held for 200ms after all supplies become valid. also asserted after pbr is held low for more than 2 seconds and for an additional 200ms after pbr is released. srst (pin 7): soft reset. active low, open-drain logic output with weak pull-up to v cc3 . can be pulled up greater than v cc3 when interfacing to 5v logic. asserted for 100 m s after pbr is held low for less than 2 seconds and released. pbr (pin 8): push-button reset. active low logic input with weak pull-up to v cc3 . can be pulled up greater than v cc3 when interfacing to 5v logic. when asserted for less than 2 seconds, outputs a soft reset 100 m s pulse on the srst pin. when pbr is asserted for greater than 2 seconds, the rst output is forced low and remains low until 200ms after pbr is released. v cc3 (pin 1): 3.3v sense input and power supply pin for the ic. bypass to ground with 3 0.1 m f ceramic capacitor. v cc5 (pin 2) (ltc1326): 5v sense input. used as gate drive for the rst output fet when the voltage on v cc3 is less than the voltage on v cc5 . if unused, it can be tied to v cc3 (see dual and single supply monitor operation in the applications information section). v cc25 (pin 2) (ltc1326-2.5): 2.5v sense input. used as gate drive for rst output fet when the voltage on v cc3 is less than the voltage on v cc25 . if unused it can be tied to v cc3 . v cca (pin 3): 1v sense, high impedance input. can be used as a logic input with a 1v threshold. if unused it can be tied to either v cc3 or v cc25 . gnd (pin 4): ground. rst (pin 5): reset logic output. active high cmos logic output, drives high to v cc3 , buffered complement of rst. an external pull-down on the rst pin will drive this pin high. pi n fu n ctio n s uuu
7 ltc1326/ltc1326-2.5 block diagra s w ltc1326 + + + + + 25mv v cc3 v cc3 internal 4.15v v cc3 soft reset reset 25mv 3 v cca 1 v cc3 2 v cc5 8 pbr 7 m a 6 m a 6 m a 7 srst 4 gnd ref pbr timer 200ms reset generator v cc3 6 rst 5 v cc3 rst 1326 bd v cc3 + v cc3 v cc5 power detect/ gate drive to power detect ltc1326-2.5 + + v cc3 internal v cc3 soft reset reset to power detect v cc3 v cc25 3 v cca 1 v cc3 2 v cc25 8 pbr 7 m a 6 m a 6 m a 7 srst 4 gnd ref pbr timer 200ms reset generator power detect/ gate drive v cc3 6 rst 5 v cc3 rst 1326-2.5 bd v cc3 +
8 ltc1326/ltc1326-2.5 the three internal precision voltage comparators have response times that are typically 13 m s. this slow re- sponse time helps prevent mistriggering due to tran- sients on each of the v cc inputs. the parts ability to suppress transients can be improved by bypassing each of the v cc inputs with a 0.1 m f capacitor to ground. push-button reset the parts provide a push-button reset input pin. the pbr input has an internal pull-up current source to v cc3 . if the pbr pin is not used it can be left floating. when the pbr is pulled low for less than t pb ( ? 2 sec), a narrow (100 m s typ) soft reset pulse is generated on the srst output pin after the button is released. the push- button circuitry contains an internal debounce counter which delays the output of the soft reset pulse by typically 20ms. this pin can be or-tied to the rst pin and issue what is called a soft reset. the srst thereby resets the microprocessor without interrupting the dram refresh cycle. in this manner dram information remains undis- turbed. alternatively, srst may be monitored by the processor to initiate a software-controlled reset. when the pbr pin is held low for longer than t pb ( ? 2 sec), a standard reset is generated on the rst and rst pins. once the 2 second period has elapsed, a reset signal is produced by the push-button logic, thereby clearing the reset counter. once the button is released, the reset counter begins counting the reset period (200ms nomi- nal). consequently, the reset outputs remain asserted for approximately 200ms after the button is released. ti i g diagra s w w u applicatio s i for atio wu u u operation the ltc1326/ltc1326-2.5 are micropower, high accu- racy triple supply monitoring circuits. the parts have two basic functions: generation of a reset when power sup- plies are out of range, and generation of reset or a soft reset when the pbr pin is pulled low. supply monitoring all three v cc inputs must be above predetermined thresholds for 200ms before the reset output is released. the parts will assert reset during power-up, power-down and brownout conditions on any one or more of the v cc inputs. on power-up, either the v cc5 or v cc3 pin on the ltc1326, or the v cc25 or v cc3 pin on the ltc1326-2.5, can power the drive circuits for the rst pin. this ensures that rst will be low when v cc5 , v cc25 or v cc3 reaches 1v. as long as any one of the v cc inputs is below its predetermined threshold, rst will stay a logic low. once all of the v cc inputs rise above their thresholds, an internal timer is started and rst is released after 200ms. the rst pin outputs the inverted state of what is seen on rst pin. rst is reasserted whenever any one of the v cc inputs drops below its predetermined threshold and remains asserted until 200ms after all of the v cc inputs are above their thresholds. on power-down, once any of the v cc inputs drop below its threshold, rst is held at a logic low. a logic low of 0.4v is guaranteed until v cc3 and v cc5 on the ltc1326 or v cc3 and v cc25 on the ltc1326-2.5 drop below 1v. push-button reset function timing t < t pb t pb t rst t db t srst 1326 /2.5 td02 pbr rst srst t rst 1326 /2.5 td01 v rtx v ccx rst v cc monitor timing
9 ltc1326/ltc1326-2.5 during a supply induced reset condition, the ability of the pbr pin to force a soft reset condition on the srst pin is disabled. in other words srst will remain high. if the pbr pin is held low, both during and after a supply induced reset (low rst), the rst pin will remain low until 200ms after the pbr goes high. power detect/gate drive the ltc1326/ltc1326-2.5 for the most part are powered internally from the v cc3 pin. the exception is at the gate drive of the output fet on the rst pin. on the input to this fet is power detection circuitry used to detect and drive the gate from either the 3.3v input pin (v cc3 ) or the 5v input pin (v cc5 ) on the ltc1326 or the 2.5v input pin (v cc25 ) on the ltc1326-2.5. the gate drive is derived from the pin with the highest potential. this ensures the part pulls the rst pin low as soon as either input pin is 3 1v. early versions of the ltc1326 did not have the power detect/gate drive circuitry. these early versions were powered off of v cc3 alone. consult factory for date codes concerning this circuitry change. all date codes of the ltc1326-2.5 have the power detect/gate drive circuits. dual and single supply monitor operation the v cc3 , v cc5 and v cca inputs may be individually disabled by the following override techniques which allow the ltc1326 or ltc1326-2.5 to be used as a dual or single supply monitor. ltc1326 override functions the v cca pin, if unused, can be tied to either v cc3 or v cc5 . this is an obvious solution since the trip points for v cc3 and v cc5 will always be greater than the trip point for v cca . the v cc5 input trip point is disabled if its voltage is equal to the voltage on v cc3 25mv and the voltage on v cc5 is less than 4.15v. in this manner the part will behave as a 3.3v monitor and the v cc5 reset will be disabled. the v cc5 trip point is reenabled when the voltage on v cc5 is equal to the voltage on v cc3 25mv and the two inputs are greater than approximately 4.15v. in this manner the ltc1326 can function as a 5v monitor with the 3.3v monitor disabled. when monitoring either 3.3v or 5v with v cc3 strapped to v cc5 , (see figure 1) the ltc1326 determines which is the appropriate range. the ltc1326 handles this situation as shown in figure 2. above 1v and below v rt3 , rst is held low. from v rt3 to approximately 4.15v the ltc1326 assumes 3.3v supply monitoring and rst is deasserted. above approximately 4.15v the ltc1326 operates as a 5v monitor. in most systems the 5v supply will pass through the 3.1v to 4.15v region in <200ms during power-up, and the rst output will behave as desired. table 1 summarizes the state of rst and rst at various operating voltages with v cc3 = v cc5 . applicatio s i for atio wu u u table 1. override truth table (v cc3 = v cc5 ) inputs (v cc3 = v cc5 = v cc ) rst rst 0v v cc 1v 1v v cc v rt3 01 v rt3 v cc 4.15v 1 0 4.15v v cc v rt5 01 v rt5 v cc 10 figure 2. rst voltage vs supply voltage 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1326 system reset r2 1326 /2.5 f01 r1 adjustable supply 3.3v or 5v 4.7k figure 1 supply voltage (v) 0 rst output voltage (v) 3 4 5 4 1326 /2.5 f02 2 1 0 1 2 3 5 v cc3 = v cc5 = v cca = 0v to 5v 4.7k pull-up from rst to v cc3
10 ltc1326/ltc1326-2.5 figure 3 contains a simple circuit for 5v systems that cant risk the rst output going high in the 3.1v to 4.15v range (possibly due to very slow rise time on the 5v supply). diode d1 powers the ltc1326 while dropping ? 0.6v from the v cc5 pin to the v cc3 pin. this prevents the parts internal override circuit from being activated. without the override circuit active, the rst pin stays low until v cc5 reaches v rt5 @ 4.725v. (see figure 4.) ltc1326-2.5 override functions the v cca pin, if unused, can be tied to either v cc3 or v cc25 . this is an obvious solution since the trip points for v cc3 and v cc25 will always be greater than the trip point for v cca . likewise, the v cc25 , if unused, can be tied to v cc3 . v cc3 must always be used. tying v cc3 to v cc25 and operating off of a 2.5v supply will result in the continuous assertion of rst. extending esd tolerance on the pbr input pin the pbr pin is susceptible to esd since it may be brought out to a front panel in normal applications. the esd tolerance of this pin can be increased by adding a resistor in series with the pbr pin. a 10k resistor can increase the esd tolerance of the pbr pin to approximately 10kv. the pbrs internal pull-up current of 7 m a typical means there is only 70mv (150mv max) dropped across the resistor. see figure 5. applicatio s i for atio wu u u push-button reset 1 2 3 4 8 7 6 5 v cc3 v cc25 v cca gnd pbr srst rst rst ltc1326-2.5 3.3v system reset 2.5v r2 r1 1326 /2.5 f05 adjustable supply or dc/dc feedback divider 10k* *optional resistor extends esd tolerance of pbr input to approximately 10kv figure 5. triple supply monitor (3.3v, 2.5v and adjustable) with extended esd tolerance 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1326 system reset 1326 /2.5 f03 5v 0.1 f 4.7k d1* *mmbd914 or equivalent v cc5 (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 rst output voltage (v) 1326/2.5 f04 5 4 3 2 1 0 v cc5 = v cca = 0v to 5v 4.7k pull-up from rst to v cc5 t a = 25 c figure 3. ltc1326 monitoring a single 5v supply. d1 used to avoid rst high near 3.3v to 4v (see figure 2). figure 4. rst output voltage characteristics of the circuit in figure 3
11 ltc1326/ltc1326-2.5 typical applicatio n s n u triple supply monitor (3.3v, 5v and adjustable) 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1326 3.3v system reset 5v r2 r1 1326 /2.5 ta03 adjustable supply or dc/dc feedback divider dual supply monitor (3.3v or 5v plus adj) refer to ltc1326 override functions in the applications information section. 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1326 system reset r2 1326 /2.5 f01 r1 adjustable supply 3.3v or 5v 4.7k 1 2 3 4 8 7 6 5 v cc3 v cc25 v cca gnd pbr srst rst rst ltc1326-2.5 system reset r2 1326 /2.5 ta07 r1 adjustable supply 3.3v 4.7k dual supply monitor (3.3v plus adj) dual supply monitor (3.3v and 5v, defeat v cca input) 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1326 3.3v system reset 5v 1326 /2.5 ta05
12 ltc1326/ltc1326-2.5 typical applicatio n s n u srst tied to rst and or-tying other sources to rst to generate reset and reset 4.7k srst 6 m a 6 m a 3.3v ltc1326/ ltc1326-2.5 pushbutton reset reset 1326 /2.5 ta08 other open drain reset sources or-tied to reset 7 8 pbr rst rst v cc3 6 5 using v cca tied to dc/dc feedback divider 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1326 3.3v system reset 5v 22.1k 1% 1326 /2.5 ta09 35.7k 1% ltc1435 adjustable reset trip threshold 2.74v 2.9v 2.8k 1% 6 v osense using the short pulse width, push-button soft reset feature to initiate hard reset 1 2 3 4 8 7 6 5 v cc3 v cc25 v cca gnd pbr srst rst rst ltc1326-2.5 3.3v reset 2.5v pbr 20ms rst 1326 /2.5 ta11 200ms 40ns t p 10 m s
13 ltc1326/ltc1326-2.5 typical applicatio n s n u monitoring a negative supply 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1326 5v ?v 3.3v c2 0.1 f system reset 1326 /2.5 ta12 r1 150k 1% r3 100k 1% v cca r2 150k 1% r4 392k 1% c1 0.1 f q1 2n3906 q3 2n3904 q2 2n3906 r4 ? (100k)(0.98)(v trip + 0.55)(?) 1 2 3 4 8 7 6 5 v cc3 v cc25 v cca gnd pbr srst rst rst ltc1326-2.5 2.5v system reset r2 1326 /2.5 ta13 r1 adjustable supply 3.3v 100k reset valid for v cc3 down to 0v v cc3 (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 rst output voltage (v) 1326/2.5 ta13a 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v cc3 = v cc25 = v cca t a = 25 c rst output with 100k pull-up to v cc3 rst output without 100k pull-up. 10m load to gnd supply v trip r4 C 5v C 4.6v 392k C 3.3v C 3v 237k C 12v C 10.8v 1m
14 ltc1326/ltc1326-2.5 ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660) msop (ms8) 1197 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" (0.152mm) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.040 0.006 (1.02 0.15) 0.012 (0.30) ref 0.006 0.004 (0.15 0.102) 0.034 0.004 (0.86 0.102) 0.0256 (0.65) typ 12 3 4 0.192 0.004 (4.88 0.10) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102) package descriptio u dimensions in inches (millimeters) unless otherwise noted.
15 ltc1326/ltc1326-2.5 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** package descriptio u dimensions in inches (millimeters) unless otherwise noted.
16 ltc1326/ltc1326-2.5 ? linear technology corporation 1998 132625f lt/tp 1198 4k ? printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com triple supply monitor with 3.3v and 5v system resets 1 2 3 4 8 7 6 5 v cc3 v cc5 v cca gnd pbr srst rst rst ltc1326 3.3v to 3.3v system reset 10k 10k to 5v system reset q1 2n7002 5v r2 r1 1326 /2.5 ta14 adjustable supply or dc/dc feedback divider part number description comments ltc690 5v supply monitor, watchdog timer and battery backup 4.65v threshold ltc694-3.3 3.3v supply monitor, watchdog timer and battery backup 2.9v threshold ltc699 5v supply monitor and watchdog timer 4.65v threshold ltc1232 5v supply monitor, watchdog timer and push-button reset 4.37v/4.62v threshold ltc1536 precision triple supply monitor for pci applications meets pci t fail timing specifications related parts typical applicatio u

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